Coarse Delay - 2.6 English

Coarse delay allows the adjusting of the delay in the digital datapath which can be useful to compensate for delay mismatch in a system implementation. The compensation here is limited to some period of the sampling clock. For PCB design and flight time information for correct delay adjustment, see the UltraScale Architecture PCB Design User Guide (UG583). The following table shows the number of periods of the sampling clock (T1 or T2 = 2*T1) for this delay tuning capability for Gen 1/Gen 2 devices.

The following table shows the number of periods of the sampling clock (T1) for this delay tuning capability for Gen 3/DFE devices.