Dual RF-DAC I/Q Input to Real Output (Gen 3/DFE) - 2.6 English

Figure 1. RF-DAC I/Q Input to Real Output

Figure 2. Dual RF-DAC I/Q Input to Real Output IP Core Configuration

The following figure shows a Dual RF-DAC with I/Q input to real output, 2x interpolation, the mixer bypassed, and running at a 400 MHz AXI4-Stream clock. The input consists of 16 samples per AXI4-Stream cycle (8 I and 8 Q words).

Figure 3. Dual RF-DAC I/Q Input to Real Output Timing (Gen 3/DFE)