RF-ADC Decimation Filters (Gen 3/DFE) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2024-05-30
Version
2.6 English

The following diagram shows the decimation stages in Gen 3/DFE devices.

Figure 1. Decimation Filters Hierarchy (Gen 3/DFE)

There are four stages of decimation filters cascaded; each decimation stage can be bypassed independently. The FIR1 stage contains 3 decimation filters—FIR1a (2x), FIR1b (3x), and FIR1c (5x)—only one of them can be enabled for a specified configuration. The FIR2, FIR3, and FIR4 blocks all have a decimation factor of 2. Using a combination of filters the following shows all possible decimation factors:

1x (bypass), 2x, 3x, 4x, 5x, 6x, 8x, 10x, 12x, 16x, 20x, 24x, 40x

Note: The signal flow direction of the DDC is: FIR4->FIR3->FIR2->FIR1.

The IP configuration and driver API choose the high order FIR combinations automatically. For example, FIR2 and FIR1a are chosen for a 4x decimation.