Register Space - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2024-05-30
Version
2.6 English

The address map, shown in the following table, is split on a per-tile basis. All banks are 16 KB. The first bank contains the functions common to all tiles. Each tile has a bank for control and status.

Table 1. Address Space
AXI4-Lite Address Range ADDR[17:0] Function
0x00000 - 0x03FFF IP Common Control and Status
0x04000 - 0x07FFF RF-DAC Tile 0 registers (Tile <n> Registers)
0x08000 - 0x0BFFF RF-DAC Tile 1 registers (Tile <n> Registers)
0x0C000 - 0x0FFFF RF-DAC Tile 2 registers (Tile <n> Registers)
0x10000 - 0x13FFF RF-DAC Tile 3 registers (Tile <n> Registers)
0x14000 - 0x17FFF RF-ADC Tile 0 registers (Tile <n> Registers)
0x18000 - 0x1BFFF RF-ADC Tile 1 registers (Tile <n> Registers)
0x1C000 - 0x1FFFF RF-ADC Tile 2 registers (Tile <n> Registers)
0x20000 - 0x23FFF RF-ADC Tile 3 registers (Tile <n> Registers)
0x24000 - 0x3FFFF Reserved