On-chip PLL Clock Forwarding (Gen 3/DFE) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

The sampling clock generated by the on-chip PLL is forwarded in the RF-DAC and RF-ADC groups, respectively. Clock source has to be selected as Tile 1 or Tile 2.

Figure 1. On-chip PLL Clock Forwarding