The number of AXI4-Stream interfaces and the width of each bus depends on the bandwidth required by the mode of operation selected in the AMD Vivado™ IDE. Interpolation and decimation allow the AXI4-Stream bandwidth requirements to be reduced and the width of each AXI4-Stream interface can be selected on the IP core configuration screen in conjunction with the clock rate and interpolation/decimation settings.
See the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) for the maximum sample rate in all devices, for both RF-ADCs and RF-DACs.
The following figure shows a single RF-DAC data input at 4 GSPS with 8x interpolation with I and Q on a single AXI4-Stream interface running at 500 MHz.
The following figure shows an RF-ADC at 2 GSPS with 4x decimation with I and Q on a single AXI4-Stream interface running at 500 MHz.
The following figure shows 2x32-bit RF-DACs at 4 GSPS with real data, 8x interpolation, and running at a 250 MHz AXI4-Stream clock.
