Sub-ADC and Interleaving Factors - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

AMD uses interleaving technology to build the RF-ADCs. Each RF-ADC in a Dual RF-ADC tile consists of eight sub-ADCs, and each RF-ADC in a Quad RF-ADC tile consists of four sub-ADCs. In this document, the number of sub-ADCs mentioned as the interleaving factor is either four for the Quad RF-ADC tile or eight for the Dual RF-ADC tile. The higher the interleaving factor the higher the maximum sampling rate that the RF-ADC can support.