RF-DAC Interface Data and Clock Rates - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

The total data rate per channel to the PL is determined by a number of factors, RF-DAC sample rate, interpolation factor, and I/Q or Real data formats. The gearbox FIFOs provide a way of interfacing this data rate to the clock frequency of the PL design, by allowing the number of words per clock to be chosen. The only requirements are that the interface number of words and clock rate combine to match the data rate required by the RF-DAC channel, and all RF-DACs in a tile share a common interface clock frequency. This is shown by the following equations:

PLDataRate = (DACDataRate x IQMode) / InterpolationRate

PLFclock x PLNumWords = PLDataRate

PLFclock = PLDataRate / PLNumWords


IQMode = 1 for real digital data mode and 2 for I/Q digital data mode.

The IP core automatically calculates the data rates based on the RF-DAC sample rate and datapath settings. This is shown in the following figure.

Figure 1. RF-DAC Data Interface Data and Clock Configuration

Each tile has independent clocking; sample rates, clock rates, PL rates, and configurations can be specified on a per-tile basis.