- Tile configuration
- Four or two RF-ADCs
and one PLL per tile
- Gen 1/Gen 2: 12-bit
RF-ADC resolution, with 16-bit digital
signal processing datapath; each 12-bit data stream is MSB-aligned to 16-bit
samples at the output of the RF-ADC
core before passing to the DDC block
- Gen 3/DFE: 14-bit RF-ADC resolution, with 16-bit digital signal processing datapath; each
14-bit data stream is MSB-aligned to 16-bit samples at the output of the
RF-ADC core before passing to the
DDC block
- Implemented as either four channels (Quad) or two
channels (Dual) (the sampling rate is device dependent; for the actual
sampling rate specifications, see the
Zynq
UltraScale+ RFSoC Data Sheet: DC and AC Switching
Characteristics (DS926))
- Decimation filters
- Gen 1/Gen 2: 1x (bypass filter), 2x, 4x, 8x
- Gen 3/DFE: 1x (bypass filter), 2x, 3x, 4x, 5x, 6x, 8x,
10x, 12x, 16x, 20x, 24x, 40x
- 80% of Nyquist bandwidth, 89 dB stop-band
attenuation
- Digital Complex Mixers
- Full complex mixers support real or I/Q inputs from the
RF-ADC
- 48-bit Numeric Controlled Oscillator (NCO) per RF-ADC
- Fixed Fs/4, Fs/2 low power frequency mixing mode, where
Fs is the sample frequency
- I/Q and real input signals supported
- Single/multi-band flexibility
- 2x bands per RF-ADC
pair
- 4x bands per Quad RF-ADC tile
- Can be configured for real or I/Q inputs
- Full bandwidth of the RF-ADC
can be accessed in bypass mode
- Input signal amplitude threshold: Two programmable threshold
flags per RF-ADC
- Built-in digital correction for external analog quadrature
modulators:
- Supports gain, phase, and offset correction for an I/Q
input pair (two RF-ADCs)
- SYSREF input signal for multi-channel synchronization
- Flexible AXI4-Stream
interface supports a wide range of programmable logic clock rates and converter
sample rates
- Per tile current-mode logic (CML) clock input buffer with
on-chip calibrated 100Ω termination; supplies the RF-ADC sampling clocks or provides a reference clock for the on-chip
PLL
- Dedicated high-speed, high-performance, differential input
buffer per RF-ADC with on-chip calibrated 100Ω
termination (on-die termination)
- Output common mode reference voltage for DC-coupling RF-ADC inputs
- Gen 3/DFE: Digital Step Attenuator (DSA)
- Gen 3/DFE: Power saving mode in Time Division Duplexing (TDD)
application
- Gen 3/DFE: Different decimation factors and FIFO data rates for RX and
Observation channel in the Time Division Duplexing (TDD) application