Dual RF-ADC Real Input to Real Output - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2024-05-30
Version
2.6 English
Figure 1. Dual RF-ADC Real Input to Real Output
Figure 2. Dual RF-ADC Real Input to Real Output IP Configuration

The following figure shows a Dual RF-ADC with real data input to real data output, 1x decimation, the mixer bypassed and running at a 500 MHz AXI4-Stream clock.

Figure 3. Dual RF-ADC Real Input to Real Output Data Timing