Changes from V2.5 to V2.6 - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)
Document ID
PG269
Release Date
2024-05-30
Version
2.6 English

Parameter Changes

In version 2.6, the ability to dynamically change the fabric interface width on Gen 1 and Gen 2 designs using multi-tile synchronization has been added. This function is already available on Gen 3 and DFE designs. The following user parameters enable this feature.

Table 1. Parameter Changes in Version 2.6
Parameter Function
ADC_MTS_Variable_Fabric_Width Enable RF-ADC variable fabric width for multi-tile synchronization applications on Gen 1 and Gen 2 devices.
DAC_MTS_Variable_Fabric_Width Enable RF-DAC variable fabric width for multi-tile synchronization applications on Gen 1 and Gen 2 devices.

Port Changes

When the RF-ADC Calibration Freeze real-time signals are enabled the following ports have been added for Gen 3 and DFE devices.

Table 2. RF-ADC Port Changes in Version 2.6
Port Direction Upgrade Action
Quad RF-ADC1
adcXY_sig_detect 1 Out Leave Open
Dual RF-ADC2
adcX_ZZ_sig_detect 2 Out Leave Open
  1. X refers to the location of the tile in the converter column. Y refers to the location of the RF-ADC in the tile (0 to 3).
  2. X refers to the location of the tile in the converter column. ZZ is either 01 (the lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile)