VOP Details (Gen 3/DFE) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2024-05-30
Version
2.6 English

The following diagram shows the on-chip VOP feature.

Figure 1. VOP Overview (Gen 3/DFE)
CAUTION:
To use the VOP feature, the DAC_AVTT must be 3.0V.

The variable output power is achieved by varying the full-scale current in fine steps defined in the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926). The full scale current of the RF-DAC can be derived as follows:

  • RF-DAC full scale current (μA) = Minimum VOP Current + N * VOP step size (μA)

Where N = 0, 1, 2, …, limited by the maximum full scale current.

To avoid the potential harm to the wireless transmitter signal chain when gain changes dramatically, the API is designed to divide a large jump to several small steps then update the VOP sequentially with certain time interval. The step is approximately ±10% of the current VOP value.

The default full scale current during start-up is set by the IP configuration.