Real-Time TDD Signals for Dual RF-ADCs (Gen 3/DFE) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2024-05-30
Version
2.6 English
Table 1. Real-Time TDD Signals for Dual RF-ADCs.
Port Name 1 I/O Clock Description
adcXY_tdd_mode I s_axi_aclk Time Division Duplexing control signal. A logic high on this input will power down the channel.
  1. X refers to the location of the tile in the converter column. Y refers to the location of the DDC block in the tile (0 to 3).
  2. A TDD signal interface is added for each AXI4-Stream interface. When I/Q data is output, two interfaces are present for each RF-ADC. In this case, the adcXY_tdd_mode inputs should be tied together.