struct XRFdc_DSA_Settings (Gen 3/DFE) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2024-05-30
Version
2.6 English

This structure contains the Digital Step Attenuator settings.

u32 DisableRTS; /*Disables RTS control of DSA attenuation*/
float Attenuation; /*Attenuation*/

Description

u32 DisableRTS
This disables the real time signals from setting the attenuation
float Attenuation
The attenuation 0 - 11 dB for ES1 silicon.
The attenuation 0 - 27 dB for production silicon.