Power-on Sequence Steps - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2024-05-30
Version
2.6 English
Table 1. Power-on Sequence Numbers
Sequence Number State Description
0-2 Device Power-up and Configuration The configuration parameters set in the AMD Vivado™ IDE are programmed into the converters. The state machine then waits for the external supplies to be powered up. In hardware this can take up to 25 ms. However this is reduced to 200 μs in behavioral simulations.
3-5 Power Supply Adjustment

DAC_Tile0 and ADC_Tile0 control the bandgap trim for the device. If these tiles are enabled they should be powered up to at least stage 4 in order that the bandgap trim settings are propagated to the other enabled tiles.

The configuration settings are propagated to the analog sections of the converters. In addition the regulators, bias settings in the RF-DAC, and the common-mode output buffer in the RF-ADC are enabled.
6-10 Clock Configuration The state machine first detects the presence of a good clock into the converter. Then, if the PLL is enabled, it checks for PLL lock. The clocks are then released to the digital section of the converters.
11-13 Converter Calibration (ADC only) Calibration is carried out in the RF-ADC. In hardware this can take approximately 10 ms for Gen 1/Gen 2 and 63 ms for Gen 3/DFE. However, this is reduced to 60 μs in behavioral simulations.

In Gen 3/DFE devices, the common mode over and under voltage signals are monitored prior to the beginning of the calibration process. Both signals must be low before calibration is started.

14 Wait for deassertion of AXI4-Stream reset The AXI4-Stream reset for the tile should be asserted until the AXI4-Stream clocks are stable. For example, if the clock is provided by a MMCM, the reset should be held until it has achieved lock. The state machine waits in this state until the reset is deasserted.
15 Done The state machine has completed the power-up sequence.