- AXI Clock Frequency (MHz)
- The core requires information on the frequency of the AXI4-Lite clock input to ensure the correct timing of the power-on sequence of the RF-ADC and RF-DAC blocks. The speed of the clock should be entered in MHz. The maximum allowed frequency is given by the DRP clock maximum frequency specified in the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).