Port Name 1 | I/O | Clock | Description | |
---|---|---|---|---|
mX_axis_aclk | In | N/A | Clock input for RF-ADC data output | |
mX_axis_aresetn | In | N/A | Active-Low synchronous reset for the mX_axis_aclk domain. This should
be held low until mX_axis_aclk is stable. The reset can be asserted asynchronously but its
deassertion must be synchronous to sX_axis_aclk. This resets the RF-ADC data path and output FIFO. |
|
mXY_axis_tdata[M:0] | Out | mX_axis_aclk | AXI4-Stream data output | |
mXY_axis_tvalid | Out | mX_axis_aclk | AXI4-Stream valid | |
mXY_axis_tready | In | mX_axis_aclk | AXI4-Stream ready. Not used in IP core. | |
Quad RF-ADC Tile | vinXZ_p | In | N/A | Analog input |
vinXZ_n | In | N/A | Analog input | |
Dual RF-ADC Tile | vinX_ZZ_p | In | N/A | Analog input |
vinX_ZZ_n | In | N/A | Analog input | |
|