Real-Time Signal Interface Ports for RF-DACs - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2024-05-30
Version
2.6 English
Table 1. Real-Time Signal Interface Ports for RF-DACs
Port Name 1 I/O Clock Description
dacXZ_fast_shutdown[2:0] In N/A RF-DAC fast shutdown

001 - Scale output data by 0.5

011 - Scale output data by 0.25

111 - Scale output data by 0

Others - Normal operation

dacXY_pl_event In clk_dacX RF-DAC PL event

Assert to update RF-DAC settings from the PL.

dacXY_datapath_overflow Out Async RF-DAC datapath overflow

Asserted when a sub-block in the signal chain has detected that the output signal amplitude has exceeded full scale and has been saturated.

dacX_sysref_gate 2 In s_axi_aclk When asserted the sysref is not acted on by the RF-DAC.
dacX_sync_out 2 Out clk_dacX This is a one cycle wide pulse that asserts when a sysref event has arrived and indicates the divider values are valid.
  1. X refers to the location of the tile in the converter column. Y refers to the location of the DUC block in the tile (0 to 3). Z refers to the location of the RF-DAC in the tile (0 to 3).
  2. Gen 3/DFE only.