Sample Rate Clock Forwarding (Gen 3/DFE) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

The high frequency sample rate clock from external or generated by in-tile PLL can be forwarded within a tile group. In this case, some additional constraints are listed as following:

  • In Gen 3 devices, only RF-ADC Tile 3 and Tiles 2 are allowed to accept forwarded clock from RF-DAC tiles.
  • In DFE devices, all RF-ADC tiles are allowed to accept a forwarded clock from RF-DAC tiles.
  • Gen 3 Source Tiles: Either Tile 1 or Tile 2 (the two center tiles) can be a source tile if it has the external clock input pins.
  • DFE Source Tiles: All tiles that have external clock input pins can be a source tile.
  • In-Tile Clock Divider: Each tile has an independent clock divider by 1 or 2 available when in-tile PLL is not enabled. This in-tile clock divider is not available for dual RF-ADC tiles when the sample rate clock is forwarded from RF-DAC tiles.
  • Forwarding Path Clock Divider: A clock divider by 1 or 2 is located in the clock forwarding path. This divider is only available when forwarding sample rate clock from RF-DAC tiles to RF-ADC tiles. This clock divider has higher priority than the in-tile clock divider, which means bypass this forwarding path divider while enabling in-tile clock divider in RF-ADC tiles is not allowed.
  • Both types of clock dividers mentioned above are handled by the RFDC API and IP automatically. You should take care of the constraints of the clock dividers in the clock distribution scheme design to avoid violations.

The following figure illustrates this use case and related constraints:

Figure 1. Sample Rate Clock Forwarding

The explanation of the figure is described below:

  • There are three tile groups in the figure above:
    1. RF-DAC tile 3 and 2
    2. RF-DAC tile 1 and 0, RF-ADC tile 3 and 2
    3. RF-ADC tile 1 and 0
  • In tile group #1, RF-DAC Tile 2 receives the reference clock from external and forwards its T1 clock generated by in-tile PLL to RF-DAC Tile 3. The in-tile clock divider is not available in RF-DAC Tile 2, but is available to Tile 3.
  • In tile group #2, the RF-DAC Tile 1 receives a sampling clock from external and forwards it to RF-DAC Tile 0, RF-ADC Tile 3, and Tile 2. In-tile clock divider is available in RF-DAC Tile 1 and 0 because both have no PLL enabled. Assuming RF-ADC Tile 3 is a dual RF-ADC tile and Tile 2 is quad RF-ADC tile (this is not real case but for illustration only), there is no in-tile clock divider available in RF-ADC tile 3, but is available in RF-ADC tile 2. Remember the forwarding path divider must be 2 if any in-tile divider is enabled (set to 2) in this group.
  • In tile group #3, the RF-ADC Tile 1 and 0 of Gen 3 devices cannot receive the forwarded sample rate clock from RF-DAC tiles. This illustrates that a reference clock is forwarded from RF-ADC Tile 1 to 0. There is no in-tile clock divider available because both tiles enabled their in-tile PLLs.