Converter 3 Interrupt Enable Register (0x0224) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)
Document ID
PG269
Release Date
2024-05-30
Version
2.6 English
Table 1. Converter 3 Interrupt Enable Register (0x0224)
Bit Default Value Access Type Description
31:16 - - Reserved (read back 0)
31:20 1 - - Reserved (read back 0)
19 1 R/W Enable common mode under voltage interrupt in converter 2, 3
18 1 Enable common mode under voltage interrupt in converter 2, 3
17:16 - - Reserved (read back 0)
15 1 R/W Enable FIFO overflow interrupt in Converter
14 1 Enable datapath overflow interrupt in Converter
13 1 Enable overflow interrupt for observation channel FIFO in converter 2 , 3
12:4 - - Reserved (read back 0)
3 1 R/W Enable Over Range interrupt in converter 2
2 1 Enable Over Voltage interrupt in converter 2
1:0 - - Reserved (read back 0)
  1. 31:16 is Reserved (read back 0) for Gen 1/Gen 2 devices.
  2. RF-ADC only.
  3. Gen 3/DFE only.