- Up to 16 14-bit RF-DACs
- Gen 1/Gen 2: Four 12-bit Dual RF-ADC tiles, or four 12-bit Quad RF-ADC tiles
- Gen 3: One, two, or four 14-bit Dual RF-ADC tiles, and/or two or four 14-bit Quad RF-ADC tiles
- DFE: One or three 14-bit Dual RF-ADC tiles, and/or two 14-bit Quad RF-ADC tiles
- Supports alignment between multiple converters (Multi-Tile Synchronization (MTS))
- Pre-programmed RF-DAC and RF-ADC with key user-defined parameters
- Multiple AXI4-Stream data interfaces for RF-ADCs and RF-DACs
- Single AXI4-Lite configuration interface
- Gen 1/Gen 2: 1x (bypass), 2x, 4x, 8x decimation and interpolation
- Gen 3/DFE: 1x (bypass), 2x, 3x, 4x, 5x, 6x, 8x, 10x, 12x, 16x, 20x, 24x, 40x decimation and interpolation with additional 2x interpolation after mixer
- Digital complex mixers and Numerical Controlled Oscillator (NCO)
- Quadrature Modulation Correction (QMC)
- Gen 3/DFE: Embedded Digital Step Attenuator (DSA) for each RF-ADC, and Variable Output Power (VOP) control for each RF-DAC
- On-chip clocking system including PLL for each tile
- Gen 3/DFE: On-chip clock distribution network
- Gen 3/DFE: TDD mode support power saving mode and RX/Obs sharing mode