| Port Name 1, 2 | I/O | Clock | Description |
|---|---|---|---|
| adcXY_pl_event | In | clk_adcX |
RF-ADC PL event Assert to update RF-ADC settings from the PL. |
| adcX_ZZ_over_range | Out | Async | Over range output. A High on this output indicates that the signal exceeds the full-scale input of the RF-ADC. |
| adcX_ZZ_over_threshold1 | Out | clk_adcX | Over threshold1 output Signal amplitude level is above programmable threshold 1. |
| adcX_ZZ_over_threshold2 | Out | clk_adcX | Over threshold2 output Signal amplitude level is above programmable threshold 2. |
| adcX_ZZ_over_voltage | Out | Async | Over voltage output An Over Voltage condition occurs when a signal far exceeds the normal operating input-range. |
| adcX_ZZ_clear_or | In | s_axi_aclk | When asserted the over range is cleared. |
| adcXY_datapath_overflow | Out | Async |
RF-ADC datapath
overflow Asserted when a sub-block in the signal chain has detected that the output signal amplitude has exceeded full scale and has been saturated. |
| adcX_ZZ_clear_ov 3 | In | s_axi_aclk | When asserted the over voltage output is cleared. |
| adcX_ZZ_cm_over_voltage 3 | Out | Async | Common mode over voltage output. A High on this output indicates that the input signal common mode exceeds safe operating conditions. |
| adcX_ZZ_cm_under_voltage 3 | Out | Async | Common mode under voltage. A High on this output indicates that the input signal common mode is too low for safe operation. |
| adcX_sysref_gate 3 | In | Async | When asserted the SYSREF is not acted on by the RF-ADC. |
| adcX_sync_out 3 | Out | clk_adcX | This is a one cycle wide pulse that asserts when a sysref event has arrived and indicates the divider values are valid. |
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