Example Design - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

The following figure shows the example design that is provided with the core.

Figure 1. Example Design

The complete example design can be opened as a separate project by right-clicking the core in the project hierarchy after it has been customized using the IP catalog. Right-click the <component_name>.xci file in the Design Sources hierarchy in the Sources window and select Open IP Example Design. This opens a new AMD Vivado™ IP integrator project in a new window with a complete RF Data Converter IP example design.

The Zynq™ UltraScale+™ RFSoC RF Data Converter example design consists of the following:

  • An instance of the Zynq UltraScale+ RF Data Converter IP core
  • Data stimulus block for RF-DAC input
  • Data capture block for RF-ADC output
  • Smartconnect for AXI4-Lite addressing of the design
  • An example device-level wrapper containing BUFGs