This file contains an instantiation of the common block for the transceiver. Each of the outputs is shared by all the CPRI cores in the quad.
|
Port |
Direction |
Port on CPRI IP Core |
Description |
|---|---|---|---|
|
qpllreset_in |
In |
N/A |
PLL reset |
|
UltraScale Architecture, Virtex-7, Kintex-7, and Zynq-7000 SoC Devices |
|||
|
qpllclk_out |
Out |
qpllclk_in |
QPLL output clock |
|
qpllrefclk_out |
Out |
qpllrefclk_in |
QPLL output reference clock |
|
qplllock_out |
Out |
qplllock_in |
QPLL lock indicator (cores supporting 9,830.4 Mb/s and above only) |
|
qpllpd_in |
In |
qpll_pd |
Signal from the core used to power down the QPLL when not in use |
|
Artix-7 Devices |
|||
|
pll0outclk_out |
Out |
pll0clk_in |
PLL0 output clock |
|
pll0outrefclk_out |
Out |
pll0refclk_in |
PLL0 output reference clock |
|
pll0lock_out |
Out |
pll0lock_in |
PLL0 lock indicator |
|
pll1outclk_out |
Out |
pll1clk_in |
PLL1 output clock |
|
pll1outrefclk_out |
Out |
pll1refclk_in |
PLL1 output reference clock |
|
pll1lock_out |
Out |
pll1lock_in |
PLL1 lock indicator |