Bandwidth Timing on the MII Interface - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
Release Date
8.11 English

The Ethernet interface on the CPRI core is fixed at a data rate of 100 Mb/s in MII mode. However, the actual available bandwidth on the CPRI link varies from 0.384 Mb/s to 270.336 Mb/s, depending on link line rate and the Ethernet pointer configuration (See Table: Current Ethernet Pointer Register Current Ethernet Pointer row).

To enforce this bandwidth limit at the MII Ethernet interface, the standard CSMA/CD half-duplex collision mechanism provides rudimentary flow control. Buffering takes place within the CPRI core in both directions of the Ethernet link. When the transmit buffer is over half full, the eth_crs signal is asserted. This can be input to the carrier sense input of the Ethernet MAC to prevent further transmission. When the buffer falls below half full, eth_crs is deasserted enabling transmission to continue. When the transmission buffer is nearing the full state, the collision detect signal eth_col is asserted to provide back pressure on the Ethernet MAC. The Ethernet MAC can then attempt retransmission of the packet or, in the case of excessive retransmission attempts, drop the packet. Higher layer protocols such as TCP/IP can then attempt retransmission later.

Because the Fast C&M channel is actually a full-duplex link, the standard half-duplex collision mechanism can unnecessarily affect the throughput on the receive side of the core, corrupting a receive frame or holding off the Ethernet MAC receiver from starting a new frame. To address this, two management registers in the core are provided to allow the behavior of the collision mechanism to be slightly modified.

Setting the Ethernet Transmitter Ignore RX_DV management register to 1 means that the core does not assert the carrier sense signal eth_crs when a receive frame is being moved over the Ethernet interface. This allows simultaneous transmission of data if the Ethernet MAC only looks at CRS for transmit hold-off.

Similarly, setting the Ethernet Receiver Ignore TX_EN management register to 1 means that the receive interface does not hold off moving a frame out to the Ethernet MAC while the MAC is transmitting.

Setting both of these registers to 1 is safe in most circumstances; however, some Ethernet MACs might not behave properly with these settings. Consult your Ethernet MAC documentation to determine compatibility.