The following blocks are instantiated in the block layer.
- Encrypted RTL
- The encrypted RTL of the CPRI IP core.
- GT and Clocks (UltraScale and 7 series)
- These files instantiate the transceiver channel primitive (GT_CHANNEL) along with the RX Sync block. The RX Sync block contains logic to carry out receive phase and delay alignment. In addition, a state machine is included to program the transceiver channel clock divider settings using the Dynamic Reconfiguration Port (DRP) bus when the line rate of the link is changed.
- GT and Clocks (Versal Adaptive SoC)
- This block contains GT clock buffers, GT reset control, rate change FSMs, 64B66B Block Sync, 8B10B Encoding and Decoding, and TX & RX GT quad interfaces.
- ORI
- Optional block to support the ORI standard.
- AXI4-Lite
- Optional block to control AXI4-Lite management interface.
- RS-FEC
- Optional RS-FEC for 64b66b line rates only. See RS-FEC Enabled Mode for more information.
- 100G Ethernet RS-FEC hard block (GTYE4 transceivers only)
- Optional RS-FEC at a fixed line rate of either 24,330.24, 12,165.12, 10,137.6, or 8,110.08 Mb/s. Speed switching is currently not supported on Hard FEC implementations. This FEC can be used for up to four CPRI cores on receive only. See Hard RS-FEC Receiver for more information.