This block contains the MMCM and BUFG for the transmitter clock and a state machine to reprogram the MMCM divider settings after a speed change. In addition the receiver clock buffer for the CPRI core is instantiated. The default is to use a BUFG for the receiver clocks. However the buffer can be changed to a BUFH or a BUFR depending on the device. Table: Signal Connections for TX Clock Sharing shows the ports of the <component_name>_clocking.vhd file and the ports on the four CPRI cores to which to connect them.
|
Port |
Direction |
Port on CPRI IP Core |
Description |
|---|---|---|---|
|
stable_clk |
In |
N/A |
Management clock |
|
txoutclk_in |
In |
txoutclk from the chosen
|
TXOUTCLK from the transceiver
|
|
clk_out |
Out |
For Kintex-7, Virtex-7, and Zynq-7000 SoC device designs supporting 10,137.6 or 12,165.12 Mb/s clk_316_in port of all CPRI cores. For other designs clk_in port of all CPRI cores. |
The generated system clock |
|
refclkout |
Out |
For Kintex-7, Virtex-7, and Zynq-7000 SoC designs supporting 10,137.6 or 12,165.12 Mb/s the clk_in port of all CPRI cores. |
The generated system clock for 10,137.6 and 12,165.12 Mb/s designs |
|
rxoutclk_in |
In |
rxoutclk port of respective CPRI core |
RXOUTCLK from the transceiver |
|
recclk_out |
Out |
recclk_in port of respective CPRI core |
Recovered clock input |
|
txusrclk |
Out |
txusrclk port of all CPRI cores |
Artix-7, UltraScale, and UltraScale+ device implementations only. Provides the high frequency TXUSRCLK input to the transceiver. |
|
clk_ok |
Out |
clk_ok_in of all CPRI cores |
Derived from the lock output of the MMCM. Used to signal that the system clock is stable |
|
mmcm_reset |
In |
mmcm_rst from the chosen master CPRI core |
Signal requesting a reset of the MMCM in the clocking block. |
|
mmcm_locked |
Out |
mmcm_locked input of the CPRI cores |
In 7 series device-based cores the TXUSERRDY input of the transceiver is held Low until the MMCM has locked. |
|
txresetdone_in |
In |
txresetdone_out from the chosen master CPRI core |
Signal indicating that the reset process in the transceiver has completed. |
|
phase_alignment_done |
In |
phase_alignment_done_out output of the chosen master CPRI core. |
Asserted by the <component_name>_tx_
|
|
reset_phalignment_out |
Out |
reset_phalignment input of the <component_name>_tx_
|
Asserted to restart phase alignment after a speed change. |
|
enable |
In |
gtreset_sm_done of the chosen master CPRI core |
(GTHE2 and GTPE2 implementations only.) Asserted by the core when the transceiver reset process is complete. |
|
speed_select |
In |
stat_speed from the chosen master CPRI core |
Signal indicating the speed at which the master link is operating. |
|
mmcm_output_select[2:0] |
In |
Tie to value to select MMCM output |
(GTXE2, GTHE2 and GTPE2 implementations only.) MMCM output select. You can use a clock output other than CLKOUT0 from the MMCM. This signal should be set to reflect the MMCM output clock used to generate the core system clock. |
|
use_pll |
In |
Tie High if using the PLL in place of the MMCM |
(GTXE2, GTHE2 and GTPE2 implementations only.) pll_select as described in Static Configuration Interface . |
|
userclk_tx_reset |
In |
userclk_tx_reset output from the chosen master CPRI core |
(24,330.24, 12,165.12, and 10,137.6 Mb/s capable UltraScale architecture cores only). Asserted to reset the transmitter clock buffer. |
|
userclk_rx_reset |
In |
userclk_rx_reset output from the chosen master CPRI core |
(24,330.24, 12,165.12, and 10,137.6 Mb/s capable UltraScale architecture cores only). Asserted to reset the receiver clock buffer. |