Keep It Registered - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
Release Date
8.11 English

To simplify timing and increase system performance in an FPGA design, keep all inputs and outputs registered between your application and the core. This means that all inputs and outputs from your application should come from or connect to a flip-flop. While registering signals cannot be possible for all paths, it simplifies timing analysis and makes it easier for the Xilinx tools to place-and-route the design.