When the CPRI IP
core has been generated as a master, the core_is_master port
enables the core to switch between master and slave modes. A reset is necessary before a
change in mode takes effect.
| Port | Direction | Clock Domain | Description |
|---|---|---|---|
| core_is_master | In |
Management Clock |
(Master cores only) Defines the mode in which the core is operating. 0 - core operates as a slave 1 - core operates as a master |