The following figure shows the clock configuration for a core on a Versal adaptive SoC supporting all line rates from 2,457.6 Mb/s to 24,33024 Mb/s. 614.4 Mb/s and 1,228.8 Mb/s line rates are not supported in Versal adaptive SoC cores. In master mode, the 245.76 MHz reference clock is generated from a crystal oscillator. In slave mode, the reference clock is generated from the recovered clock using an external jitter removal PLL.
Versal adaptive SoC CPRI cores use the LCPLL to provide the clocks to the transceiver.
When the core is operating at 64b66b encoded line rates, the transceiver is configured with a 64-bit TX and RX interface and a 64-bit internal data width.
When the core is operating at 8b10b encoded line rates, the transceiver is configured with a 40-bit internal data width. This is to enable the use of the 8b10b encoding and decoding logic internal to the core. On the transmit path, the TX interface is configured in 40-bit mode. This requires the addition of a TXUSRCLK input running at twice the rate of the core clock. On the receive path, the RX interface is configured in 80-bit mode, requiring RXUSRCLK.
In slave cores, rather than routing the recovered clock directly to the external jitter-removal PLL as shown in the preceding figure, the recovered clock can be prescaled within the device to a constant nominal rate of 7.68 MHz for all line rates. The example design supplied with the core contains an example implementation of this prescaling technique.