Table: Clock and Reset Ports (Versal ACAPs) lists the clock and reset ports on the CPRI core when using Versal™ ACAP. It is important to note that CPRI cores using Versal ACAPs do not have a shared logic support layer.
|
Port |
Direction |
Description |
|---|---|---|
|
reset |
In |
Active-High asynchronous reset for the core. This reset is synchronized to each clock domain inside the core. It does not reset the management configuration registers. The core can also be reset using a soft reset (see General Configuration and Transmit CPRI Alarms Register (0xE) ). Soft reset also does not reset the management configuration registers. |
|
aux_clk/
|
In |
Management clock in the range 5-125 MHz. When the AXI4-Lite Management Interface option is selected, the management interface is clocked by the s_axi_aclk input from the AXI4-Lite bus. When the generic management interface is used, the aux_clk input is used to clock the management interface. See Customizing and Generating the Core for more information. This clock can be shared between multiple instances of the CPRI core. |
|
reset_aux_clk/
|
In |
Management Interface reset. Asserting this signal resets the management sections of the design. reset_aux_clk is for generic management interface, s_axi_aresetn is generated when the AXI4-Lite Management interface option is selected. |
|
hires_clk |
In |
High resolution sampling clock used to measure the transit time of the clock-domain crossing FIFO(s). Must be at least 150 MHz when operating at speeds of 2,457.6 Mb/s and under 175 MHz for 3,072 Mb/s operation 275 MHz for 4,915.2 Mb/s operation 325 MHz for operation at 6,144 and 9,830.4 Mb/s 380 MHz for operation at 8,110.08, 10,137.6, 12,165.12 and 24,330.24 Mb/s. The clock should not be derived from the same source as refclk ; it must be unrelated. This clock can be shared between multiple instances of the CPRI core. |
|
hires_clk_ok |
In |
High resolution clock OK. Signal indicating the status of the high resolution clock. Set High when the clock is stable. |
|
eth_ref_clk |
In |
Ethernet clock running at 25 MHz. When the MII interface is selected, this clock is used to clock the Ethernet interface. This should also be used to clock the client logic attached to this interface. |
|
eth_tx_clk |
In |
Ethernet transmit clock running at 125 MHz. When the GMII interface is selected, this clock is used to clock the transmit side of the Ethernet interface. This should also be used to clock the client logic attached to the transmit interface. |
|
eth_rx_clk |
In |
Ethernet receive clock running at 125 MHz. When the GMII interface is selected, this clock is used to clock the receive side of the Ethernet interface. This should also be used to clock the client logic attached to the receive interface. |
|
txoutclk |
In |
Transmit clock from the Versal GT Quad to the CPRI IP core. This is used to generate the system clock. |
|
rxoutclk |
In |
Receive clock from the Versal GT Quad to the CPRI IP core. This is used to generate the recovered clock. |
|
txusrclk_gt |
Out |
Transmit user clock output to the Versal GT Quad. |
|
rxusrclk_gt |
Out |
Receive user clock output to the Versal GT Quad. |
|
tx_usrclk_out |
Out |
Transmit user clock for external logic. |
|
rx_usrclk_out |
Out |
Receive user clock for external logic. |
|
tx_usrclk_ok |
Out |
Signal indicating the status of the tx_usrclk_out . High indicates the clock is stable. |
|
rx_usrclk_ok |
Out |
Signal indicating the status of the rx_usrclk_out . High indicates the clock is stable. |