E-UTRA I/Q Module - 8.12 English - PG056

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2024-12-13
Version
8.12 English

The E-UTRA IQ module (contained in iq_module_eutra.vhd) provides E-UTRA I/Q multiplexing and de-multiplexing as defined in the CPRI Specification v7.0. The module is implemented as a wrapper around the UTRA-FDD I/Q Module, enabling the transmission and reception of multiple samples per channel. It multiplexes and de-multiplexes up to eight channels each with up to eight samples per basic frame period. The existence, width, and number of samples in each channel are configurable at synthesis time. The generics of the E-UTRA I/Q Module are described in the following table.

Table 1. E-UTRA I/Q Module Generics
Name Type Description
C_TX_S_n Natural Number of samples in IQ channel n (n=1…8) in the output CPRI stream. Legal values are 1-8 for active channels and 0 for inactive channels.
C_TX_WIDTH_n Natural Width of transmit IQ channel n (n=1…8) in the output CPRI stream. Legal values are 4-20 for active channels and 0 for inactive channels.
C_RX_S_n Natural Number of samples in IQ channel n (n=1…8) in the input CPRI stream. Legal values are 1-8 for active channels and 0 for inactive channels.
C_RX_WIDTH_n Natural Width of receive IQ channel n (n=1…8) in the input CPRI stream. Legal values are 4-20 for active channels and 0 for inactive channels.
Table 2. E-UTRA I/Q Module Signals - Core Interface
Port Direction Clock Domain Description
iq_tx Out System Clock IQ Transmit Data
iq_tx_enable In System Clock Transmit enable indicating start of new Tc.
iq_rx In System Clock IQ Receive Data
basic_frame_first_word In System Clock Start of new basic frame asserted once every Tc.
speed_select In System Clock Currently selected line rate. Connect to stat_speed output of CPRI core.
Table 3. E-UTRA I/Q Module Signals - Transmit Interface
Port Direction Clock Domain Description
iq_tx_i_n[C_TX_WIDTH_n -1:0] In System Clock I data for transmit direction (n = 1 to 8).
iq_tx_q_n[C_TX_WIDTH_n -1:0]   System Clock Q data for transmit direction (n = 1 to 8).
iq_tx_data_enable_n Out System Clock Data enable for transmit direction (n = 1 to 8). Asserted for C_TX_S_n cycles every Tc.

All ports of the transmit interface are synchronous to clk. The transmit interface receives the iq_tx_enable pulse from the core and outputs an iq_tx_data_enable pulse for each channel. The iq_tx_data_enable pulse is c_tx_s_n samples long. The module captures the samples sent during the iq_tx_data_enable pulse and routes them to ports on the internal UTRA-FDD I/Q Module. The assembled data is transmitted on the next basic frame.

The timing on the I/Q Data Interface is illustrated in the following figure. The number of samples must be, at most, one cycle less than the length of the basic frame. For example, at 614 Mb/s with a 16-bit IQ interface the basic frame is eight cycles long. The maximum number of samples per channel in this case is 7.

Figure 1. E-UTRA I/Q Module Transmit Timing
Table 4. E-UTRA I/Q Module Signals - Receive Interface
Port Direction Clock Domain Description
iq_rx_i_n[C_RX_WIDTH_n -1:0] Out System Clock I data for receive direction (n = 1 to 8).
iq_rx_q_n[C_RX_WIDTH_n -1:0] Out System Clock Q data for receive direction (n = 1 to 8).
iq_rx_data_valid_n Out System Clock Receive data valid. This signal is asserted for C_RX_S_n cycles every Tc, framing the samples from channel n.

The receiver interface receives the data from the internal UTRA-FDD I/Q Module along with a basic_frame_first_word pulse. It de-multiplexes the data from the internal module and outputs it along with an iq_rx_data_valid_n signal for each channel.

The timing on the I/Q Data Interface is illustrated in the following figure. As with the transmitter, the number of samples should be, at most, one cycle less than the length of the basic frame.

Figure 2. E-UTRA I/Q Module Receive Timing

The following figure shows an example of the E-UTRA wrapper transmit data mapping. In this example there are two E-UTRA channels. Channel 1 has three samples of width 14 and channel 2 has two samples of width 6.

Figure 3. E-UTRA I/Q Module Transmit Example

The first sample in channel 1 (S1A) is mapped to the channel 1 IQ inputs of the UTRA-FDD I/Q Module, the second sample (S1B) to channel 2, and the third (S1C) to channel 3. The samples from the second E-UTRA channel are mapped to channels 4 and 5 of the UTRA-FDD module. The sizes and start positions of the data in the UTRA-FDD module are set in the E-UTRA wrapper.

In this example the first eight 16-bit words of the transmitted CPRI frame appear as shown in the following figure, when the core is operating at 1,228.8 Mb/s. The samples are transmitted in order starting with those from channel 1 (S1A, S1B, S1C) followed by the samples from channel 2 (S2A, S2B).

Figure 4. E-UTRA Transmit Frame Example

The receiver performs the inverse operation of the transmitter, taking the data from the internal UTRA-FDD Module and mapping it to up to eight sample streams. The following figure shows the first eight 16-bit words of a CPRI frame received at 1,228.8 Mb/s.

Figure 5. E-UTRA Receive Frame Example

The frame contains data from three channels. The first consists of two I/Q samples of 8-bits, the second two I/Q samples of 12-bits and the third three I/Q samples of 5 bits. The following figure shows how the E-UTRA module configures the UTRA-FDD module and builds up the three sample streams.

Figure 6. E-UTRA I/Q Module Receive Example
Important: Ensure that all the samples for each channel can fit into the basic frame. If this is not the case, the data can not be correctly transmitted or received.