Supporting Line Rates up to 3,072.0 Mb/s and 6,144 Mb/s - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

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8.11 English

This Figure shows the clock configuration for a core on an UltraScale™ architecture-based device. In master mode, the reference clock is generated from a crystal oscillator. In slave mode the reference clock is generated from the recovered clock using an external jitter removal PLL.

Figure 4-8: Core Clock Configuration at 3,072.0/6,144.0 Mb/s (UltraScale Architecture)

X-Ref Target - Figure 4-8


In slave cores, rather than routing the recovered clock directly to the external jitter-removal PLL as shown in This Figure , the recovered clock can be prescaled within the device to a constant nominal rate of 30.72 MHz for all line rates.The example design supplied with the core contains an example implementation of this prescaling technique.

Note: For slave cores the external jitter-removal PLL must free-run in the absence of a reference signal; a PLL that turns off in the absence of a reference causes the transceiver to fail to start up. Contact your local System I/O specialist for guidance in selecting a PLL for your application.