This is only applicable to selected UltraScale+ devices. Refer to UltraScale Architecture and Product Data Sheet: Overview (DS980) [Ref 16] for details.
IMPORTANT: The Hard FEC sub-core (CMAC) must be placed in the same SLR of the device as the GTYE4 transceiver to guarantee timing closure. See UltraScale and UltraScale+ FPGAs Packaging and Pinouts (UG575) [Ref 17] and Zynq UltraScale+ Device Packaging and Pinouts (UG1075) [Ref 18] for details. See Constraining the Core .
When the CPRI IP core has the Use Hard FEC Receiver option enabled, interfaces are provided to access the Hard FEC. There are three possible use cases for the Hard FEC.
1. Hard FEC instantiated inside the CPRI IP core. If the Include Shared Logic in core option is selected, the CPRI IP core uses channel 0 of the instantiated Hard FEC. Three external Hard FEC interfaces (ch1, ch2, and ch3) are provided for external CPRI cores to connect to the shared Hard FEC in the CPRI core. The port list for this use case is shown in Table: Hard RS-FEC Receiver Interface Signals Channels 1, 2, and 3 - Shared Logic in the Core where x refers to external CPRI channels 1, 2, or 3.
2. Hard FEC instantiated outside of the CPRI IP core (example design). If the Include Shared Logic in example design option is selected, the CPRI IP core provides a single Hard FEC interface which can be connected to a Hard FEC instantiated in the example design or to an external CPRI core with a Hard FEC inside (use case 1). The port list for this use case is shown in Table: Hard RS-FEC Interface Signals - Shared Logic in the Example Design .
This Figure shows an example of Hard FEC sharing using the two types of CPRI IP core described above.
3. Standalone Hard FEC wrapper IP core. If the Generate a Hard FEC CPRI wrapper option is selected, a standalone Hard FEC wrapper IP core is generated instead of a CPRI IP core. This provides 4 CPRI channels for external CPRI cores to share. These can be either Xilinx CPRI IP cores or third party CPRI cores. The port list for this use case is shown in Table: Hard FEC Wrapper IP Interface Signals where x refers to CPRI channels 0, 1, 2, or 3.
IMPORTANT: Table: Hard RS-FEC Receiver Interface Signals Channels 1, 2, and 3 - Shared Logic in the Core is for CPRI cores which have a Hard FEC wrapper instantiated within them and are sharing the other 3 channels with 3 external CPRI cores.
|
Port |
Direction |
Clock Domain |
Description |
|---|---|---|---|
|
rx_rsfec_enable_chx |
In |
rx_rec_clk_chx |
Hard FEC wrapper channel enable input from CPRI lanes 1-3. Drive High to enable each CPRI channel through the RS-FEC. |
|
rx_rec_clk_chx |
In |
N/A |
Recovered clock from CPRI lanes 1-3. |
|
rx_serdes_data_chx(63:0) |
In |
rx_rec_clk_chx |
64-bit data from CPRI lanes 1-3. |
|
rx_serdes_head_chx(1:0) |
In |
rx_rec_clk_chx |
2-bit header from CPRI lanes 1-3. |
|
rx_gbx_slip_chx |
Out |
rx_rec_clk_chx |
Receive gearbox slip output to GTs in CPRI lanes 1-3. Slips the GT gearbox contents when pulsed High. |
|
cdc_reset_chx |
In |
System Clock |
Hold CDC FIFO in reset until clocks are stable. |
|
fifo_fill_level_chx(8:0) |
In |
Management Clock |
In master cores the starting level of the CDC FIFO can be set using this input port. By default, the CDC FIFO fills to fill_level=64 before reading is enabled. To reduce latency, at the expense of reduced cable length support, the FIFO fill level can be reduced. |
|
average_chx(16:0) |
Out |
hires_clk |
Averaged CDC FIFO transit time value. This value can be converted to UI by multiplying by 66 and dividing by 256. |
|
average_rdy_chx |
Out |
hires_clk |
Averaged CDC FIFO transit time value ready. Handshake signal used for transferring the CDC average value from the source clock domain to the destination clock domain of the external CPRI cores 1-3. |
|
average_ack_chx |
In |
Management Clock |
Averaged CDC FIFO transit time value acknowledge. Handshake signal used for transferring the CDC average value from the source clock domain to the destination clock domain of the external CPRI cores 1-3. |
|
fifo_error_chx |
Out |
System Clock |
Indicates a FIFO full or FIFO empty condition. This will cause cdc_reset to assert. |
|
cdc_rxdata_chx(63:0) |
Out |
System Clock |
64-bit data from Hard FEC wrapper to CPRI lanes 1-3. This is the data from the read port of the CDC FIFO and is intended to be used by the receiving CPRI core for non-FEC line rates. |
|
cdc_rxheader_chx(1:0) |
Out |
System Clock |
2-bit header from Hard FEC wrapper to CPRI lanes 1-3. This is the header from the read port of the CDC FIFO and is intended to be used by the receiving CPRI core for non-FEC line rates. |
|
pcs_txclk_chx |
Out |
N/A |
System Clock from the host CPRI core to external CPRI lanes 1-3. The output data and header is synchronous to this clock. |
|
pcs_txclk_ok_chx |
Out |
N/A |
System Clock from the host CPRI core to external CPRI lanes 1-3 is stable. |
|
pcs_rxdata_chx(63:0) |
Out |
System Clock |
64-bit data from Hard FEC wrapper to CPRI lanes 1-3. |
|
pcs_rxheader_chx(1:0) |
Out |
System Clock |
2-bit header from Hard FEC wrapper to CPRI lanes 1-3. |
|
pcs_rxheadervalid_chx |
Out |
System Clock |
This output indicates the start of a codeword on CPRI lanes 1-3. |
|
stat_rx_aligned_status_chx |
Out |
System Clock |
When High, this signal indicates that alignment to the incoming codeword boundary position has been achieved and the receiver is accepting and processing data. |
|
stat_cw_inc_chx |
Out |
System Clock |
Active-High pulse Indicates a received RS-FEC codeword. |
|
stat_corrected_cw_inc_chx |
Out |
System Clock |
Active-High pulse Indicates a corrected RS-FEC codeword. |
|
stat_uncorrected_cw_inc_
|
Out |
System Clock |
Active-High pulse Indicates an uncorrected RS-FEC codeword. |
|
hfec_fifo_latency_chx(15:0) |
Out |
System Clock |
Variable latency through the Hard FEC to the external CPRI cores 1, 2, and 3. This value can be used to perform the delay measurement calculation described in Delay Measurement and Requirement 21 (R21) in hardware. The value is the number of rx_fast_clk clock cycles. Multiply by 66 to get the latency in UI. |
|
hfec_fifo_latency_rdy_chx |
Out |
System Clock |
Hard FEC FIFO Latency ready signal. Handshake signal used for clock domain crossing the latency value from the host CPRI core to the external CPRI cores 1, 2, and 3. |
|
hfec_fifo_latency_ack_chx |
In |
Management Clock (Channel 1-3) |
Hard FEC FIFO Latency acknowledge signal. Handshake signal used for clock domain crossing the latency value from the host CPRI core to the external CPRI cores. |
Table: Hard RS-FEC Interface Signals - Shared Logic in the Example Design is for CPRI cores which do not have a Hard FEC wrapper instantiated within them and are sharing a channel of a Hard FEC wrapper in an external CPRI core.
|
Port |
Direction |
Clock Domain |
Description |
|---|---|---|---|
|
rx_rsfec_enable_ch |
Out |
rx_rec_clk_ch |
Hard FEC wrapper channel enable to the Hard FEC in the host CPRI core. Driven high by the core to enable the CPRI channel. |
|
rx_rec_clk_ch |
Out |
N/A |
Recovered clock to the Hard FEC in the host CPRI core. |
|
rx_serdes_data_ch(63:0) |
Out |
rx_rec_clk_ch |
64-bit data to the Hard FEC in the host CPRI core. |
|
rx_serdes_head_ch(1:0) |
Out |
rx_rec_clk_ch |
2-bit header to the Hard FEC in the host CPRI core. |
|
rx_gbx_slip_ch |
In |
rx_rec_clk_ch |
Receive gearbox slip input from the Hard FEC to the CPRI GT. Slips the GT gearbox contents when pulsed high. |
|
cdc_reset_ch |
Out |
pcs_txclk_ch |
Hold CDC FIFO in reset until clocks are stable. |
|
fifo_fill_level_ch(8:0) |
Out |
Management Clock |
In master cores, the starting level of the CDC FIFO can be set using this output port. By default the CDC FIFO fills to fill_level=64 before reading is enabled. To reduce latency, at the expense of reduced cable length support, the FIFO fill level can be reduced. |
|
average_ch(16:0) |
In |
hires_clk |
Averaged CDC FIFO transit time value. This value can be converted to UI by multiplying by 66 and dividing by 256. |
|
average_rdy_ch |
In |
hires_clk |
Averaged CDC FIFO transit time value ready. Handshake signal used for transferring the CDC average value from the source clock domain to the destination clock domain of the CPRI channel. |
|
average_ack_ch |
Out |
Management Clock |
Averaged CDC FIFO transit time value acknowledge. Handshake signal used for transferring the CDC average value from the source clock domain to the destination clock domain of the CPRI channe l. |
|
fifo_error_ch |
In |
pcs_txclk_ch |
Indicates a FIFO full or FIFO empty condition. This will cause cdc_reset_ch to assert |
|
cdc_rxdata_ch(63:0) |
In |
pcs_txclk_ch |
64-bit data from Hard FEC wrapper to the CPRI channel. This is the data from the read port of the CDC FIFO and is intended to be used by the receiving CPRI core for non-FEC line rates. |
|
cdc_rxheader_ch(1:0)
|
In |
pcs_txclk_ch |
2-bit header from Hard FEC wrapper to the CPRI channel. This is the header from the read port of the CDC FIFO and is intended to be used by the receiving CPRI core for non-FEC line rates. |
|
pcs_txclk_ch |
In |
N/A |
Recovered clock from the Hard FEC wrapper to the CPRI channel. |
|
pcs_txclk_ok_ch |
In |
N/A |
Recovered clock from the Hard FEC wrapper to the CPRI channel is stable. |
|
pcs_rxdata_ch(63:0) |
In |
pcs_txclk_ch |
64-bit data from Hard FEC wrapper to the CPRI channel. |
|
pcs_rxheader_ch(1:0) |
In |
pcs_txclk_ch |
2-bit header from Hard FEC wrapper to the CPRI channel. |
|
pcs_rxheadervalid_ch |
In |
pcs_txclk_ch |
This output indicates the start of a codeword on the CPRI channel. |
|
stat_rx_aligned_status_ch |
In |
pcs_txclk_ch |
When High this signal indicates that alignment to the incoming codeword boundary position has been achieved and the receiver is accepting and processing data. |
|
stat_cw_inc_ch |
In |
pcs_txclk_ch |
Active-High pulse Indicates a received RS-FEC codeword. |
|
stat_corrected_cw_inc_ch |
In |
pcs_txclk_ch |
Active-High pulse Indicates a corrected RS-FEC codeword. |
|
stat_uncorrected_cw_inc_ch |
In |
pcs_txclk_ch |
Active-High pulse Indicates an uncorrected RS-FEC codeword. |
|
hfec_fifo_latency_ch(15:0) |
In |
pcs_txclk_ch |
Variable latency through the Hard FEC to the external CPRI core. This value can be used to perform the delay measurement calculation described in Delay Measurement and Requirement 21 (R21) in hardware. The value is the number of rx_fast_clk clock cycles. Multiply by 66 to get the latency in UI. |
|
hfec_fifo_latency_rdy_ch |
In |
pcs_txclk_ch |
Hard FEC FIFO Latency ready signal. Handshake signal used for clock domain crossing the latency value from the host CPRI core to the external CPRI core. |
|
hfec_fifo_latency_ack_ch |
Out |
Management Clock |
Hard FEC FIFO Latency acknowledge signal. Handshake signal used for clock domain crossing the latency value from the host CPRI core to the external CPRI core. |