Note: The Transceiver Data Monitor Interface is not available when using
Versal adaptive SoC.
The transmit and receive data at the transceiver fabric interface are on this interface. The signals described in the following table are used to monitor the transceiver input and output for debug purposes. These signals are output when the Additional Transceiver Control and Status Ports option is selected on the Vivado CPRI core customization screen.
| Port | Direction | Clock Domain | Description |
|---|---|---|---|
| txusrclk2 | Out | N/A | In 7 series devices supporting 64B66B encoded line rates this is the main synchronization clock for all signals into the TX side of the transceiver. The transmit data and control signals, txdata, txcharisk, txheader, and txsequence are synchronous to this clock. |
| txdata | Out | Clock | Transmit data. 64 bits wide in cores with 64-bit datapath, 32 bits wide in cores with 32-bit datapath, 16 bits wide otherwise. |
| txcharisk | Out | Clock | Transmit control. High when sending an 8B/10B comma control character. 4 bits wide in cores with a 32-bit datapath, 2 bits wide otherwise. Not valid when running at 8,110.08, 10137.6, 12,165.12, or 24,330.24 Mb/s. |
| txheader[1:0] | Out | Clock | Transmit 64B/66B header. Valid only when running at 8,110.08, 10137.6, 12,165.12, or 24,330.24 Mb/s. |
| txsequence[6:0] | Out | Clock | Transmit 64B/66B sequence. Valid only when running at 8,110.08, 10137.6, 12,165.12, or 24,330.24 Mb/s. |
| rxdata | Out | Recovered Clock | Receive data. 64 bits wide in cores with 64-bit datapath, 32-bits wide in cores with 32-bit datapath, 16-bits wide otherwise. |
| rxchariscomma | Out | Recovered Clock | Receive comma. High when an 8B/10B comma control character is in the data. 4 bits wide in cores with 32-bit datapath, 2 bits wide otherwise. Not valid when running at 8,110.08, 10137.6, 12,165.12, or 24,330.24 Mb/s. |
| rxcharisk | Out | Recovered Clock | Receive control. High when an 8B/10B control character is in the data. 4 bits wide in cores with 32-bit datapath, 2-bits wide otherwise. Not valid when running at 8,110.08, 10137.6, 12,165.12, or 24,330.24 Mb/s. |
| rxdisperr | Out | Recovered Clock | Receive disparity error. High when an 8B/10B disparity error has occurred. 4 bits wide in cores with a 32-bit datapath, 2 bits wide otherwise. Not valid when running at 8,110.08, 10137.6, 12,165.12, or 24,330.24 Mb/s. |
| rxnotintable | Out | Recovered Clock | Receive not in table error. High when the received data is not a valid 8B/10B code word. 4 bits wide in cores with 32-bit datapath, 2 bits wide otherwise. Not valid when running at 8,110.08, 10137.6, 12,165.12, or 24,330.24 Mb/s. |
| rxheader[1:0] | Out | Recovered Clock | Receive 64B/66B header. Valid only when running at 8,110.08, 10137.6, 12,165.12, or 24,330.24 Mb/s. |
| rxdatavalid | Out | Recovered Clock | Receive 64B/66B data valid. High when 64B/66B data is valid. Valid only when running at 8,110.08, 10137.6, 12,165.12, or 24,330.24 Mb/s. |
| rxheadervalid | Out | Recovered Clock | Receive 64B/66B header valid. High when the 64B/66B header is valid. Valid only when running at 8,110.08, 10137.6, 12,165.12, or 24,330.24 Mb/s. |
| rxgearboxslip | Out | Recovered Clock | Receive 64B/66B rxgearboxslip. Slips gearbox contents when
High. See the
UltraScale Architecture GTY Transceivers User Guide
(UG578) and the
UltraScale
Architecture GTH Transceivers User Guide (UG576). Valid only when running at
8,110.08, 10137.6, 12,165.12, or 24,330.24 Mb/s. Disabled when running in FEC Enabled mode line rates. The FEC performs its own alignment. |