Transmit CDC FIFO - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

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8.11 English

In cores supporting 12,165.12 and 10,137.6 Mb/s implemented on Zynq-7000 SoC, Kintex-7, and Virtex-7 devices, a clock-domain crossing FIFO is present in the transmit path. The operation of this FIFO is identical to the receiver FIFO described in this section. This FIFO is not present in UltraScale architecture designs.

The transit time of data across the FIFO is held in bits 13 to 0 of the Transmit FIFO transit time register (see Table: Management Register Addresses ).