Core I/Q Interface - 8.12 English - PG056

CPRI LogiCORE IP Product Guide (PG056)
Document ID
PG056
Release Date
2024-12-13
Version
8.12 English

The transmit delay for the I/Q interface is shown in the following figure. A data word is clocked into the CPRI core on the client-side interface, and below that the first encoded data bit from that word is sent on the output pin of the transceiver. Ttx is the delay between those two events.

Figure 1. Transmit Delay, Raw I/Q Interface

The overall delay Ttx is made up of the contributions listed in the following table. Unless stated these delays are for a GTYE3 transceiver-based implementation.

For other transceiver-based implementations, the calculation is similar but uses the transceiver latencies for the relevant device.

Table 1. Contributions to Transmit Delay, GTYE3 Transceiver
Contribution Delay
  16-bit cores up to 3,072.0 Mb/s 16-bit cores up to 4,915.2/6,144.0 Mb/s 32-bit cores up to 9,830.4 Mb/s 32-bit cores up to 10,137.6 Mb/s 64-bit cores up to 24,330.24 Mb/s

FPGA logic

(TCORETX)

 40 UI 80 UI 160 UI 132 UI 396 UI
TX gearbox delay (TTGB) N/A Read back TX gearbox latency from the management interface and convert to UI as described in performing the cable delay calculation.

GTYE3 transceiver

delay (TGTYTX)

 99 UI 99 UI 189 UI 190 UI 352 UI
Total (TTX) 139 UI 179 UI 349 UI 322 UI + TGB 748 UI + TTGB

The receive delay for the raw I/Q interface is shown in the following figure. The figure shows the first encoded bit of a data word being received by the transceiver, and the corresponding data word being clocked out of the CPRI core on the raw I/Q receive interface. Trx is the delay between those events.

Figure 2. Receive Delay, Raw I/Q Interface

The following table lists the contributions that comprise the overall delay Trx.

Table 2. Contributions to Receive Delay GTYE3 Transceiver
Contribution Delay
  16-bit cores up to 3,072.0 Mb/s

16-bit cores up to

4,915.2/6,144.0 Mb/s

 32-bit cores up to 9,830.4 Mb/s 32-bit cores up to 10,137.6 Mb/s 64-bit cores up to 24,330.24 Mb/s

GTYE3 transceiver

delay (TGTYRX)

 134.5 UI 134.5 UI 256.5 UI 129.5 UI 225.5 UI

Barrel shift

(TBARREL)

 Read back barrel shift latency in UI from the management interface. N/A
RX gearbox delay (TRGB) N/A Read back RX gearbox latency from the management interface and convert to UI as described in performing the cable delay calculation.

RX CDC FIFO

transit time

(TFIFO)

 Read back RX CDC FIFO transit time from the management interface and convert to UI as described in Delay Across the CDC FIFO.

FPGA logic

(TCORERX)

 60 UI 80 UI 160 UI 165 UI 396 UI
Total (TRX) 194.5 UI + TBARREL + TFIFO 214.5 UI + TBARREL + TFIFO 416.5 UI + TBARREL + TFIFO 294.5 UI + TRGB + TFIFO 621.5 UI + TRGB + TFIFO