These documents provide supplemental material useful with this product guide:
- CPRI Specification v7.0, October 9, 2015
- 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)
- 7 Series FPGAs GTP Transceivers User Guide (UG482)
- UltraScale Architecture GTH Transceivers User Guide (UG576)
- UltraScale Architecture GTY Transceivers User Guide (UG578)
- 7 Series FPGAs Clocking Resources User Guide (UG472)
- 32G Fibre Channel (32GFC) Reed-Solomon Forward Error Correction LogiCORE IP Product Guide (PG257) (registration required)
- Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
- Vivado Design Suite User Guide: Designing with IP (UG896)
- Vivado Design Suite User Guide: Getting Started (UG910)
- Vivado Design Suite User Guide: Logic Simulation (UG900)
- ISE to Vivado Design Suite Migration Guide (UG911)
- UltraScale Architecture Migration: Methodology Guide (UG1026).
- Vivado Design Suite User Guide: Programming and Debugging (UG908)
- IEEE Std. 802.3-2015 (standards.ieee.org/getieee802/)
- UltraScale Architecture and Product Data Sheet: Overview (DS890)
- UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification (UG575)
- Zynq UltraScale+ Device Packaging and Pinouts Product Specification User Guide (UG1075)
- 7 Series FPGAs SelectIO Resources User Guide (UG471)
- UltraScale Architecture SelectIO Resources User Guide (UG571)
- Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973)
- Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331)
- Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)
- Versal Adaptive SoC Transceiver Subsystem Product Guide (PG442)
- Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)
- IEEE 1914.3-2018 IEEE Standard for Radio over Ethernet (https://ieeexplore.ieee.org/document/8486937)