MII Interface - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2022-11-16
Version
8.11 English

The MII Ethernet interface on the CPRI core is designed to appear as an MII-compliant physical-side (PHY) interface; therefore, it can be directly connected to a 100 Mb Ethernet MAC (such as the Xilinx Ethernet MAC core).

The available Ethernet data rate on the MII interface is dependent on the CPRI link speed. See Bandwidth Timing on the MII Interface for details on using the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) half-duplex collision mechanism to provide data rate control. If the Ethernet MAC does not support half-duplex mode, care must be taken to avoid exceeding the maximum Ethernet data rate for the selected CPRI line rate. Standard MII interfacing is used, as shown in Table: Ethernet Interface Signals, MII Interface , This Figure , and This Figure .

This Figure and This Figure show two frames. The first is transmitted and received without error. The second is subject to a collision due to the CPRI core transmitting and receiving at the same time. In this case the Ethernet Transmitter Ignore RX_DV and Ethernet Receiver Ignore TX_EN control bits are Low. The transmitter asserts the eth_col line to signal the collision to the client. The receiver asserts the eth_rx_er line and forces a jam pattern onto the eth_rxd output.

See Bandwidth Timing on the MII Interface for more details. If an error is received during normal operation, the receiver truncates the frame by deasserting eth_rx_dv. It then asserts eth_rx_er for one clock cycle after the deassertion of the data valid signal.

Table 3-21: Ethernet Interface Signals, MII Interface

Port

Direction

Clock Domain

Description

eth_txd[3:0]

In

Ethernet Clock

Ethernet transmit data

eth_tx_en

In

Ethernet Clock

Ethernet transmit enable

eth_tx_er

In

Ethernet Clock

Ethernet transmit error

eth_rxd[3:0]

Out

Ethernet Clock

Ethernet receive data

eth_rx_dv

Out

Ethernet Clock

Ethernet receive data valid

eth_rx_er

Out

Ethernet Clock

Ethernet receive data error

eth_rx_ready

In

Ethernet Clock

Signal from the client to the CPRI core indicating that it is ready to receive Ethernet frames. Tie High if no flow control required.

eth_rx_avail

Out

Ethernet Clock

Signal from the CPRI core indicating that it has at least one Ethernet frame ready to send to the client. Leave open if no flow control is required.

rx_fifo_almost_full

Out

Ethernet Clock

CPRI receive Ethernet FIFO is over 62.5% full.

rx_fifo_full

Out

Ethernet Clock

CPRI receive Ethernet FIFO is full.

eth_col

Out

Async

Ethernet collision detect. Asserted when the TX FIFO is full or if both the RX and TX interfaces are active and the “Ethernet Transmitter Ignores RX_DV” bit in the General Configuration and Transmit CPRI Alarms register is set to zero.

eth_crs

Out

Async

Ethernet carrier sense. Asserted when the TX interface is active or the Ethernet FIFO is over 62.5% full. In addition this signal is asserted when the RX interface is active and the “Ethernet Transmitter Ignores RX_DV” bit in the General Configuration and Transmit CPRI Alarms register is set to zero.

X-Ref Target - Figure 3-56

Figure 3-56: Transmit MII Ethernet Timing Showing a Collision
timing_ethernet_tx.jpg

X-Ref Target - Figure 3-57

Figure 3-57: Receive MII Ethernet Timing Showing an Error Due to a Collision
timing_ethernet_rx.jpg