Frame and Synchronization Interface - 8.12 English

Frame and Synchronization Interface - 8.12 English - PG056

CPRI LogiCORE IP Product Guide (PG056)

Document ID

PG056

Release Date

2024-12-13

Version

8.12 English

The synchronization interface indicates the current Universal Mobile Telecommunications System (UMTS) Node B Frame Number (BFN). The signals of this interface are shown in the following table. The length of a single UMTS frame is 10 ms and is synchronized to the system clock of the I/Q data interface, clk. Synchronization can be achieved by combining the BFN and the I/Q data interface clocks.

Table 1. Frame Synchronization Interface Port Signals
Port	Direction	Clock Domain	Description
nodebfn_tx_strobe	In	System Clock	Frame strobe in transmit direction. Synchronous to clk.
nodebfn_tx_nr[11:0]	In	System Clock	Node B Frame Number in transmit direction. Synchronous to clk.
nodebfn_rx_strobe	Out	System Clock	Frame strobe in receive direction. Synchronous to clk.
nodebfn_rx_nr[11:0]	Out	System Clock	Node B Frame Number in receive direction. Synchronous to clk.

In the transmit direction nodebfn_tx_strobe must be asserted for T_c and the BFN value in signal nodebfn_tx_nr must be maintained through the duration of the Node B Frame, as shown in the following figure. Asserting nobebfn_tx_strobe forces the next basic frame to be transmitted to be basic frame 0. It is the responsibility of the user logic to assert the nodebfn_tx_strobe signal every 10 ms as shown.

Figure 1. Frame Synchronization Timing - Transmit

To better illustrate the frame-level synchronization, the following figure shows some of the signals involved in frame transmission and their relative timing.

Figure 2. Transmit Interface Timing Relationships

The preceding figure shows the end of the assertion of the nodebfn_tx_strobe signal and shows the /COMMA/ (or in the case of 64b66b encoded line rates the /S/ character) character being transmitted at the beginning of the first basic frame of the Node B frame. It also illustrates that the vendor_tx_ns and vendor_tx_xs outputs indicate the basic frame to be transmitted next, not the basic frame being currently transmitted.

The delay through the transmit path in cores supporting up to 3,072.0 Mb/s is one clock cycle, as shown in the preceding figure. In cores supporting higher line rates, the delay through the transmit section of the core is increased to two clock cycles. This is to ensure the higher clock speed requirements in these cores are met.

On the receive side, the frame strobe nodebfn_rx_strobe is generated at the clk rising edge for T_c and the frame number is presented to the user logic at the same time. Because the CPRIcore cannot completely identify the BFN in progress until it is partially through receiving the frame, the frame number on nodebfn_rx_nr is the number of the previous frame at the time the frame strobe is asserted. This is illustrated in the following two figures.

Important: The frame number is not valid at start-up until an entire hyperframe has been received by the core.

Figure 3. Frame Synchronization Timing - Receive

Figure 4. Receive Interface Timing Relationships

The preceding figure shows the reception of the beginning of basic frame 0 at the start of a Node B frame. It shows that nodebfn_rx_strobe is asserted while basic frame 0 is being received. Also the outputs vendor_rx_ns and vendor_rx_xs indicate the transition between the last basic frame in the hyperframe completing and the start of the first basic frame.

Both of these frame synchronization interfaces are involved in the round trip delay measurement feature of the core. If the C_R21_TIMER generic is set to TRUE a timer, the R21 coarse timer, is present in the core. See Delay Measurement and Requirement 21 (R21) for more details on the round trip delay calculation.

In the master, the timer is started when the /COMMA/ (or /S/ Character for 64B66B encoded line rate) synchronization character is transmitted; this occurs when nodebfn_tx_strobe and iq_tx_enable are asserted. At this time the nodebfn_tx_nr value is stored. The timer is stopped when the master detects the start of the 10 ms CPRI frame at the receiver, corresponding to the rising edge of the nodebfn_rx_strobe, and the received nodebfn_rx_nr matches the stored nodebfn_tx_nr value.

Similarly in the slave the timer is started, and the nodebfn_rx_nr stored, when the slave receives the synchronization byte at the start of the CPRI 10 ms frame. This corresponds to the rising edge of nodebfn_rx_strobe. The timer is stopped when nodebfn_tx_strobe and iq_tx_enable are asserted and the nodebfn_tx_nr frame number matches the stored nodebfn_rx_nr.

Section 4.2.9 of CPRI Specification v7.0 shows how the delay calibration works in a CPRI system. The CPRI master core in the REC outputs a synchronization /COMMA/ character when nodebfn_tx_strobe and iq_tx_enable are asserted. This starts the R21 coarse timer in the master. When the slave core in the RE receives the synchronization character, it asserts nodebfn_rx_strobe. This starts the R21 coarse timer in the slave.

In the RE the nodebfn_rx_strobe is routed back to the nodebfn_tx_strobe input of the slave. The received frame number is also looped back to the nodebfn_tx_nr input. However, the current frame number is not output on nodebfn_rx_nr until some way into the frame. If the frame number is incrementing by one every 10 ms, then logic in the RE should increment the nodebfn_rx_nr value by one before it is input to nodebfn_tx_nr on the falling edge of nodebfn_tx_strobe.

When the CPRI slave in the RE sees nodebfn_tx_strobe and iq_tx_enable asserted, its R21 coarse timer is stopped and a /COMMA/ synchronization character is transmitted. When the CPRI master in the REC receives the synchronization character, it stops its R21 coarse timer. From the timer values and the known latencies through the system, the delay across the CPRI link can be measured.