CPRI Specific Checks - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

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8.11 English

The following section lists some tips for debugging common problems with the CPRI link.

Confirming the link stays up and there are no alarms. Do this by looking at the stat_code and stat_speed signals. Ensure that stat_alarm is not active.

Confirm that the transceiver settings are correct for the design. Check all errata and answer records for the transceiver and ensure all patches are applied.

Confirm that MMCM/PLL settings are correct for the design. Check all errata and answer records for the MMCM/PLL and ensure all patches are applied.

Check which silicon is being used, for example is it ES silicon or production? Check all errata and answer records for the silicon.

Look at the clk_ok_out and recclk_ok outputs from the core. Are these steady at logic High? The clocks can be unreliable until this is the case.

Using the debug feature, view the received data and control signals at the output of the transceiver. If errors are present in the received data, it could indicate an issue with the link. For 8B/10B line rates the signals of note are rxdata , rxcharisk , rxchariscomma and rxcharerr in the core suppport layer. For 64B/66B line rates, along with rxdata , the rxheader and rxheadervalid signals are also of note. These signals are synchronous to the recovered clock.

Check the settings for “static configuration interface” inputs to the core and ensure they meet your design requirements. See Static Configuration Interface .

Ensure the hfnsync signal is High to confirm hyperframe synchronization has been achieved

Confirm that the transmit and receive strobes are exactly 10 ms apart. The strobes at the slave end of the link should be connected as described in Frame and Synchronization Interface .

Set the core into PMA loopback (Write 0x8 to register 0x8 (AXI register 0x20)) and ensure the core can reach the operational state and data can be sent and received.