The following ports have been added in version 8.11 (2020.2) of the core. The new ports are only present in Versal™ ACAP-based cores and belong to the Transmit and Receive GT IP Interfaces.
|
Port |
Direction |
Upgrade Action |
|---|---|---|
|
ch_txmstdatapathreset |
Out |
Leave open |
|
ch_rxmstdatapathreset |
Out |
Leave open |
The following ports have been added in version 8.11 (2020.1) of the core. Port aux_clk_out has been added to Versal ACAP-based cores when the AXI management interface is selected. Port agn_line_speed is only present in cores when Agnostic mode is selected.
|
Port |
Direction |
Upgrade Action |
|---|---|---|
|
agn_line_speed(14:0) |
In |
Tie to 0 |
|
aux_clk_out |
Out |
Leave open |
The following interfaces have been added in version 8.11 (2019.2) of the core. The new interfaces are only present in Versal ACAP-based cores. For a full list of the ports in the TX and RX Versal ACAP Transceiver interfaces, refer to the section Transceiver Interfaces (Versal ACAP Cores Only) .
|
Interfaces |
Direction |
Upgrade Action |
|---|---|---|
|
TX_GT_IP_INTERFACE input ports |
In |
Tie to 0 |
|
TX_GT_IP_INTERFACE output ports |
Out |
Leave open |
|
RX_GT_IP_INTERFACE input ports |
In |
Tie to 0 |
|
RX_GT_IP_INTERFACE output ports |
Out |
Leave open |
The following ports have been added in version 8.11 (2019.2) of the core. The new ports are only present in Versal ACAP-based cores.
|
Port |
Direction |
Upgrade Action |
|---|---|---|
|
gtpowergood |
In |
Tie to 0 |
|
encommaalign |
Out |
Leave open |
|
loopback[2:0] |
Out |
Leave open |