For UltraScale and 7 Series Devices - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

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8.11 English

The CPRI core is generated as encrypted RTL along with unencrypted block layer and core support layer wrapper files. The encrypted RTL contains the transmit and receive logic, control and management interfaces, L1 synchronization logic and management registers. The block layer connects the encrypted RTL to an instance of the transceiver channel. In addition optional interfaces for AXI4-Lite management and Open Radio Equipment Interface (ORI) support are provided. The core support layer contains logic to connect the block layer to the transceiver common block and the clocking and reset logic required to implement a single CPRI link. This Figure shows a diagram of the CPRI core.

Figure 2-3: UltraScale and 7 Series – Block Level of the CPRI Core with Core Support Layer

X-Ref Target - Figure 2-3