<component_name>_resets.vhd - 8.12 English - PG056

CPRI LogiCORE IP Product Guide (PG056)
Document ID
PG056
Release Date
2024-12-13
Version
8.12 English

This file contains the reset logic for the transceiver common block.

Table 1. Signal Connections for Transceiver Common Block Resets
Port Direction Port on CPRI IP Core Description
aux_clk In N/A Management Clock
reset In N/A System Reset
qpll_reset Out

qpllreset_in port of the

<component_name>_gt_common block

 Reset for the quad PLL