The management interface is implemented as a generic, processor-friendly, memory-mapped register block that enables easy connection to either an internal processor (such as the AMD MicroBlaze™ soft processor) or to an off-chip processor.
The management interface signals are described in the following table, and the timing is illustrated in the following two figures.
mgmnt_req
signal
must be deasserted for at least one clock cycle between accesses; back-to-back transactions
are not permitted.Port | Direction | Clock Domain | Description |
---|---|---|---|
mgmnt_addr | In | Management Clock | Management Address Bus. See Management Register Map for address definitions. This port is 8 bits wide when 24,330.24 Mb/s operation is supported, 5 bits wide when 4,915.2, 6,144.0, 9,830.4, 10,137.6, or 12,165.12 Mb/s operation is supported and 4 bits wide otherwise. |
mgmnt_req | In | Management Clock | Management Request |
mgmnt_rnw | In | Management Clock | Management Read/Not Write When 1, read from management block When 0, write to management block |
mgmnt_wr_data[31:0] | In | Management Clock | Management Write Data |
mgmnt_ack | Out | Management Clock | Management Acknowledge |
mgmnt_rd_data[31:0] | Out | Management Clock | Management Read Data |
l1_timer_expired | In | Management Clock | L1 Timer Expired flag |
The core provides an input port, l1_timer_expired
, to allow the connection of a Layer 1 Timer (not
supplied with core). According to Clause 4.5.2 of the CPRI specification, this timer should be started upon entry of the
start-up procedure and cleared when the C&M channel is established (that is, when bit 3
of stat_code is set; see Status and Alarm Interfaces).
When the l1_timer_expired
input is set to 1, the start-up state machine in the CPRI core returns to State B, “Attempting L1 Synchronization” (shown
as transition 16 in the CPRI specification) and the stat_code
output becomes 0001. The l1_timer_expired
input should then be set to 0 to allow the start-up procedure
to restart.
If a level 1 timer is not implemented in the user
logic then the l1_timer_expired
port should be tied Low to
allow the start-up procedure to complete.