The following figure shows the clock configuration for a CPRI core on an Artix 7 device. In master mode, the reference clock is generated from a crystal oscillator. In slave mode the reference is generated from the recovered clock by an external jitter-removal PLL.
The recovered clock is routed to the CPRI core through a BUFH. The BUFG on the TXOUTCLK output of the transceiver can be replaced by a BUFH in
larger Artix 7 devices. See the
7
Series FPGAs Clocking Resources User Guide (UG472) for details.
The core can use either PLL0 or PLL1 from the
GTPE2_COMMON block. The pll_select input to the core should
be set to 01 when using PLL0 and to 10 when using PLL1.
In slave cores, rather than routing the recovered clock directly to the external jitter removal PLL as shown in the preceding figure, the recovered clock can be prescaled within the FPGA to a constant nominal rate of 30.72 MHz for all line rates. The example design supplied with the core contains an example implementation of this prescaling technique.