Hard FEC Constraints - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

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8.11 English

When a Hard FEC is generated inside the core, the GTYE4 transceiver and Hard FEC (CMAC) must be located in the same SLR of the device to achieve timing closure. Do not try to connect the CMAC to transceiver channels through an SLR crossing. See U ltraScale and UltraScale+ FPGAs Packaging and Pinouts ( UG575) [Ref 17] and Zynq UltraScale+ Device Packaging and Pinouts (UG1075) [Ref 18] for details.