When a Hard FEC is generated inside the core, the GTYE4 transceiver and Hard FEC (CMAC) must be located in the same SLR of the device to achieve timing closure. Do not try to connect the CMAC to transceiver channels through an SLR crossing. See UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification (UG575) and Zynq UltraScale+ Device Packaging and Pinouts Product Specification User Guide (UG1075) for details.