Hard FEC Wrapper IP Core Interface - 8.11 English

rx_fast_clk

In

N/A

Hard FEC wrapper clock 368.64 MHz, used on the 66bit ingress and egress datapaths.

rx_fast_reset

In

rx_fast_clk

Hard FEC wrapper reset. Active-High input.

hires_clk

In

N/A

High resolution sampling clock used to measure the transit time of the clock domain crossing FIFOs. Must be at least 380 MHz.

rsfec_clk

In

N/A

RS-FEC clock input:

• 294.912 MHz for 24.3G Hard FEC cores

• 184.32 MHz for 12.1G Hard FEC cores

• 153.6MHz for 10.1G Hard FEC cores

• 122.88MHz for 8.1G Hard FEC cores

• For 24.3G Hard FEC cores this clock should be generated from the rx_fast_clk (368.64MHz).

• For 12.1G, 10.1G and 8.1G Hard FEC cores this clock should be the same as the rx_fast_clk.

all_clk_locked

In

N/A

Assert High when rx_fast_clk, rsfec_clk and hires_clk input clocks are all stable.

rsfec_enable_correction

In

rx_fast_clk

When set High, enables FEC correction.

rsfec_enable_indication

In

rx_fast_clk

When set High, enables FEC indication of total CWs and corrected and uncorrected CWs.

rx_rsfec_enable_chx

In

rx_rec_clk_chx

Hard FEC wrapper channel enable input from CPRI lanes 0-3. Drive high to enable each CPRI channel through the RS-FEC.

rx_rec_clk_chx

In

N/A

Recovered clock from CPRI lanes 0-3.

rx_serdes_data_chx(63:0)

In

rx_rec_clk_chx

64-bit data from CPRI lanes 0-3.

rx_serdes_head_chx(1:0)

In

rx_rec_clk_chx

2-bit header from CPRI lanes 0-3.

rx_gbx_slip_chx

Out

rx_rec_clk_chx

Receive gearbox slip output to GTs in CPRI lanes 0-3. Slips the GT gearbox contents when pulsed high.

cdc_reset_chx

In

rx_fast_clk

Hold CDC FIFO in reset until clocks are stable.

fifo_fill_level_chx(8:0)

In

Management Clock

In master cores the starting level of the CDC FIFO can be set using this input port. By default the CDC FIFO fills to fill_level=64 before reading is enabled. To reduce latency, at the expense of reduced cable length support, the FIFO fill level can be reduced.

average_chx(16:0)

Out

hires_clk

Averaged CDC FIFO transit time value. This value can be converted to UI by multiplying by 66 and dividing by 256.

average_rdy_chx

Out

hires_clk

Averaged CDC FIFO transit time value ready.Handshake signal used for transferring the CDC average value from the source clock domain to the destination clock domain of the external CPRI cores 0-3. ⁽³⁾

average_ack_chx

In

Management Clock

Averaged CDC FIFO transit time value acknowledge. Handshake signal used for transferring the CDC average value from the source clock domain to the destination clock domain of the external CPRI cores 0-3. ⁽³⁾

fifo_error_chx

Out

rx_fast_clk

Indicates a FIFO full or FIFO empty condition. This will cause cdc_reset to assert.

cdc_rxdata_chx(63:0)

Out

rx_fast_clk

64-bit data from Hard FEC wrapper to CPRI lanes 0-3. This is the data from the read port of the CDC FIFO is intended to be used by the receiving CPRI core for non-FEC line rates.

cdc_rxheader_chx(1:0)

Out

rx_fast_clk

2-bit header from Hard FEC wrapper to CPRI lanes 0-3. This is the header from the read port of the CDC FIFO and is intended to be used by the receiving CPRI core for non-FEC line rates.

pcs_rxdata_chx(63:0)

Out

rx_fast_clk

64-bit data from Hard FEC wrapper to CPRI lanes 0-3.

pcs_rxheader_chx(1:0)

Out

rx_fast_clk

2-bit header from Hard FEC wrapper to CPRI lanes 0-3.

pcs_rxheadervalid_chx

Out

rx_fast_clk

This output indicates the start of a codeword on CPRI lanes 0-3.

stat_rx_aligned_status_chx

Out

rx_fast_clk

When High this signal indicates that alignment to the incoming codeword boundary position has been achieved and the receiver is accepting and processing data.

stat_cw_inc_chx

Out

rx_fast_clk

Active-High pulse Indicates a received RS-FEC codeword.

stat_corrected_cw_inc_chx

Out

rx_fast_clk

Active-High pulse Indicates a corrected RS-FEC codeword.

stat_uncorrected_cw_inc_chx

Out

rx_fast_clk

Active-High pulse Indicates an uncorrected RS-FEC codeword.

hfec_fifo_latency_chx(15:0)

Out

rx_fast_clk

Variable latency through the Hard FEC Wrapper to CPRI channels 0-3. This value can be used to perform the delay measurement calculation described in Delay Measurement and Requirement 21 (R21) in hardware. The value is the number of rx_fast_clk clock cycles. Multiply by 66 to get the latency in UI.

hfec_fifo_latency_rdy_chx

Out

rx_fast_clk

Hard FEC FIFO Latency ready signal. Handshake signal used for clock domain crossing the latency value from the Hard FEC wrapper to the external CPRI cores 0-3. Signal is high when the latency value is ready to be transferred.

hfec_fifo_latency_ack_chx

In

Management Clock

Channel (0-3)

Hard FEC FIFO Latency acknowledge signal. Handshake signal used for clock domain crossing the latency value from the Hard FEC wrapper to the external CPRI cores 0-3. If it is not necessary to perform clock crossing on hfec_fifo_latency_chx, these ports should be permanently driven High. Otherwise wait until ready signal is high and then pulse acknowledge High when the latency value has been transferred.

Notes:

1. Where _chx refers to external CPRI channels 0, 1, 2, or 3.

2. In hard FEC wrapper IP designs where Xilinx CPRI IP cores are not being used, the following handshake mechanism should be used to transfer the CDC FIFO average value from the hard FEC wrapper clock domain to your own CPRI core clock domain. The signal average_ack_chx should be pulsed High when average_chx(16:0) has been read by the external CPRI core. The hard FEC wrapper will then update average_chx(16:0) with a new value. When the new value is valid the hard FEC wrapper asserts High average_rdy_chx .

3. If using Xilinx CPRI IP cores the handshake logic does this automatically.