AXI4-Lite Interface Debug - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

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8.11 English

Read from a register that does not have all 0s as a default to verify that the interface is functional.

See This Figure for a read timing diagram. Output s_axi_arready asserts when the read address is valid and output s_axi_rvalid asserts when the read data/response is valid. If the interface is unresponsive ensure that the following conditions are met.

The s_axi_aclk and aclk inputs are connected and toggling.

The interface is not being held in reset, and s_axi_areset is an active-Low reset.

Ensure that the main core clocks are toggling and that the enables are also asserted.

Has a simulation been run? Verify in simulation and/or a debugging tool to capture that the waveform is correct for accessing the AXI4-Lite interface.