You can remove the transmit and receive frame buffers from the CPRI core for implementation in the user logic. This can be useful if specialized frame buffers are required. When the Bypass Ethernet Buffers option is selected, the core accepts data on the TX Ethernet interface in the AXI4-Stream format. Data is output in AXI4-Stream format on the RX Ethernet interface.
Table: Ethernet Interface Signals with Frame Buffers Bypassed gives the signals on the TX and RX Ethernet interfaces when the core is generated with the Bypass Ethernet Buffers option selected.
This Figure shows the timing on the Ethernet Transmit interface when the core is generated with the Bypass Ethernet Buffers option selected.
When a frame of Ethernet data is ready to be sent across the CPRI link tx_axis_eth_tvalid should be asserted and the first byte of data presented on the tx_axis_eth_tdata input. When the byte is accepted by the CPRI core it asserts tx_axis_eth_tready . The next byte of data should then be presented at the tx_axis_eth_tdata input. In 16-bit and 32-bit cores, the tx_axis_eth_tready output is asserted once every five system clock cycles when the transmitted subchannel is in the control and management area defined by the Ethernet pointer. In 64-bit cores the tx_axis_eth_tready signal is asserted once every two clock cycles. When the last byte of data is present at the TX interface, tx_axis_eth_tlast should be asserted. The first byte of a new frame can be transmitted in the next cycle if required, otherwise tx_axis_tvalid should be deasserted. If it is required to send an error code across the CPRI link, the tx_axis_eth_tuser input should be asserted.
This Figure shows the timing of the Ethernet data on the Receiver interface.
When the core receives the first byte of an Ethernet frame it is presented on the rx_axis_eth_tdata port, along with rx_axis_eth_tvalid . In 16-bit and 32-bit cores, during frame reception a new byte is presented once every five clock cycles when the received subchannel is within the control and management area defined by the Ethernet pointer. In 64-bit cores a new byte is presented once every two clock cycles. When the last byte of a frame is received, it is presented with the rx_axis_eth_tlast output asserted. If an error is received the core drives the rx_axis_eth_tuser output High.