Interface with Ethernet Frame Buffers Bypassed - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2022-11-16
Version
8.11 English

You can remove the transmit and receive frame buffers from the CPRI core for implementation in the user logic. This can be useful if specialized frame buffers are required. When the Bypass Ethernet Buffers option is selected, the core accepts data on the TX Ethernet interface in the AXI4-Stream format. Data is output in AXI4-Stream format on the RX Ethernet interface.

Table: Ethernet Interface Signals with Frame Buffers Bypassed gives the signals on the TX and RX Ethernet interfaces when the core is generated with the Bypass Ethernet Buffers option selected.

Table 3-23: Ethernet Interface Signals with Frame Buffers Bypassed

Port

Direction

Clock Domain

Description

tx_axis_eth_tdata[7:0]

In

System Clock

Ethernet Transmit data

tx_axis_eth_tvalid

In

System Clock

Ethernet Transmit data valid. Should be asserted when a byte of data is available to be transmitted.

tx_axis_eth_tlast

In

System Clock

Ethernet Transmit data last byte. Asserted when the last byte of a frame is present on the tx_axis_eth_tdata input.

tx_axis_eth_tuser

In

System Clock

Ethernet Transmit data error. Asserted to include an error code on the current byte.

tx_axis_eth_tready

Out

System Clock

Ethernet Transmit data ready. Asserted by the CPRI core when it has accepted the current byte of data on the tx_axis_eth_tdata input.

rx_axis_eth_tdata[7:0]

Out

System Clock

Ethernet Receive data

rx_axis_eth_tvalid

Out

System Clock

Ethernet Receive data valid. Asserted by the CPRI core when the data on the RX interface is valid.

rx_axis_eth_tlast

Out

System Clock

Ethernet Receive data last. Asserted by the CPRI core when the data output is the last byte of a frame.

rx_axis_eth_tuser

Out

System Clock

Ethernet Receive data error. Asserted by the CPRI core when the current byte contains an error code.

This Figure shows the timing on the Ethernet Transmit interface when the core is generated with the Bypass Ethernet Buffers option selected.

Figure 3-62: Transmit Ethernet Timing with Buffers Bypassed

X-Ref Target - Figure 3-62

tx_timing_buffs_bypassed.jpg

When a frame of Ethernet data is ready to be sent across the CPRI link tx_axis_eth_tvalid should be asserted and the first byte of data presented on the tx_axis_eth_tdata input. When the byte is accepted by the CPRI core it asserts tx_axis_eth_tready . The next byte of data should then be presented at the tx_axis_eth_tdata input. In 16-bit and 32-bit cores, the tx_axis_eth_tready output is asserted once every five system clock cycles when the transmitted subchannel is in the control and management area defined by the Ethernet pointer. In 64-bit cores the tx_axis_eth_tready signal is asserted once every two clock cycles. When the last byte of data is present at the TX interface, tx_axis_eth_tlast should be asserted. The first byte of a new frame can be transmitted in the next cycle if required, otherwise tx_axis_tvalid should be deasserted. If it is required to send an error code across the CPRI link, the tx_axis_eth_tuser input should be asserted.

This Figure shows the timing of the Ethernet data on the Receiver interface.

Figure 3-63: Receive Ethernet Timing with Buffers Bypassed

X-Ref Target - Figure 3-63

rx_timing_buff_bypass.jpg

When the core receives the first byte of an Ethernet frame it is presented on the rx_axis_eth_tdata port, along with rx_axis_eth_tvalid . In 16-bit and 32-bit cores, during frame reception a new byte is presented once every five clock cycles when the received subchannel is within the control and management area defined by the Ethernet pointer. In 64-bit cores a new byte is presented once every two clock cycles. When the last byte of a frame is received, it is presented with the rx_axis_eth_tlast output asserted. If an error is received the core drives the rx_axis_eth_tuser output High.